| 1 |
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| 2 |
#define BLOCKPAPI |
| 3 |
|
| 4 |
void blockpapi_addEvent(int event, char *description); |
| 5 |
void blockpapi_start(); |
| 6 |
void blockpapi_stop(); |
| 7 |
void blockpapi_writeReport(); |
| 8 |
long long *blockpapi_getValues(); |
| 9 |
void blockpapi_writeSystemInfo(); |
| 10 |
|
| 11 |
/* These define NATV_the event codes for all the native events listed by native_avail */ |
| 12 |
|
| 13 |
#define NATV_ALAT_CAPACITY_MISS_ALL 0x40000000 |
| 14 |
#define NATV_ALAT_CAPACITY_MISS_FP 0x40000001 |
| 15 |
#define NATV_ALAT_CAPACITY_MISS_INT 0x40000002 |
| 16 |
#define NATV_BACK_END_BUBBLE_ALL 0x40000003 |
| 17 |
#define NATV_BACK_END_BUBBLE_FE 0x40000004 |
| 18 |
#define NATV_BACK_END_BUBBLE_L1D_FPU_RSE 0x40000005 |
| 19 |
#define NATV_BE_BR_MISPRED_DETAIL_ANY 0x40000006 |
| 20 |
#define NATV_BE_BR_MISPRED_DETAIL_PFS 0x40000007 |
| 21 |
#define NATV_BE_BR_MISPRED_DETAIL_ROT 0x40000008 |
| 22 |
#define NATV_BE_BR_MISPRED_DETAIL_STG 0x40000009 |
| 23 |
#define NATV_BE_EXE_BUBBLE_ALL 0x4000000a |
| 24 |
#define NATV_BE_EXE_BUBBLE_ARCR 0x4000000b |
| 25 |
#define NATV_BE_EXE_BUBBLE_ARCR_PR_CANCEL_BANK 0x4000000c |
| 26 |
#define NATV_BE_EXE_BUBBLE_BANK_SWITCH 0x4000000d |
| 27 |
#define NATV_BE_EXE_BUBBLE_CANCEL 0x4000000e |
| 28 |
#define NATV_BE_EXE_BUBBLE_FRALL 0x4000000f |
| 29 |
#define NATV_BE_EXE_BUBBLE_GRALL 0x40000010 |
| 30 |
#define NATV_BE_EXE_BUBBLE_GRGR 0x40000011 |
| 31 |
#define NATV_BE_EXE_BUBBLE_PR 0x40000012 |
| 32 |
#define NATV_BE_FLUSH_BUBBLE_ALL 0x40000013 |
| 33 |
#define NATV_BE_FLUSH_BUBBLE_BRU 0x40000014 |
| 34 |
#define NATV_BE_FLUSH_BUBBLE_XPN 0x40000015 |
| 35 |
#define NATV_BE_L1D_FPU_BUBBLE_ALL 0x40000016 |
| 36 |
#define NATV_BE_L1D_FPU_BUBBLE_FPU 0x40000017 |
| 37 |
#define NATV_BE_L1D_FPU_BUBBLE_L1D 0x40000018 |
| 38 |
#define NATV_BE_L1D_FPU_BUBBLE_L1D_DCS 0x40000019 |
| 39 |
#define NATV_BE_L1D_FPU_BUBBLE_L1D_DCURECIR 0x4000001a |
| 40 |
#define NATV_BE_L1D_FPU_BUBBLE_L1D_FILLCONF 0x4000001b |
| 41 |
#define NATV_BE_L1D_FPU_BUBBLE_L1D_FULLSTBUF 0x4000001c |
| 42 |
#define NATV_BE_L1D_FPU_BUBBLE_L1D_HPW 0x4000001d |
| 43 |
#define NATV_BE_L1D_FPU_BUBBLE_L1D_L2BPRESS 0x4000001e |
| 44 |
#define NATV_BE_L1D_FPU_BUBBLE_L1D_LDCHK 0x4000001f |
| 45 |
#define NATV_BE_L1D_FPU_BUBBLE_L1D_LDCONF 0x40000020 |
| 46 |
#define NATV_BE_L1D_FPU_BUBBLE_L1D_NAT 0x40000021 |
| 47 |
#define NATV_BE_L1D_FPU_BUBBLE_L1D_NATCONF 0x40000022 |
| 48 |
#define NATV_BE_L1D_FPU_BUBBLE_L1D_STBUFRECIR 0x40000023 |
| 49 |
#define NATV_BE_L1D_FPU_BUBBLE_L1D_TLB 0x40000024 |
| 50 |
#define NATV_BE_LOST_BW_DUE_TO_FE_ALL 0x40000025 |
| 51 |
#define NATV_BE_LOST_BW_DUE_TO_FE_BI 0x40000026 |
| 52 |
#define NATV_BE_LOST_BW_DUE_TO_FE_BRQ 0x40000027 |
| 53 |
#define NATV_BE_LOST_BW_DUE_TO_FE_BR_ILOCK 0x40000028 |
| 54 |
#define NATV_BE_LOST_BW_DUE_TO_FE_BUBBLE 0x40000029 |
| 55 |
#define NATV_BE_LOST_BW_DUE_TO_FE_FEFLUSH 0x4000002a |
| 56 |
#define NATV_BE_LOST_BW_DUE_TO_FE_FILL_RECIRC 0x4000002b |
| 57 |
#define NATV_BE_LOST_BW_DUE_TO_FE_IBFULL 0x4000002c |
| 58 |
#define NATV_BE_LOST_BW_DUE_TO_FE_IMISS 0x4000002d |
| 59 |
#define NATV_BE_LOST_BW_DUE_TO_FE_PLP 0x4000002e |
| 60 |
#define NATV_BE_LOST_BW_DUE_TO_FE_TLBMISS 0x4000002f |
| 61 |
#define NATV_BE_LOST_BW_DUE_TO_FE_UNREACHED 0x40000030 |
| 62 |
#define NATV_BE_RSE_BUBBLE_ALL 0x40000031 |
| 63 |
#define NATV_BE_RSE_BUBBLE_AR_DEP 0x40000032 |
| 64 |
#define NATV_BE_RSE_BUBBLE_BANK_SWITCH 0x40000033 |
| 65 |
#define NATV_BE_RSE_BUBBLE_LOADRS 0x40000034 |
| 66 |
#define NATV_BE_RSE_BUBBLE_OVERFLOW 0x40000035 |
| 67 |
#define NATV_BE_RSE_BUBBLE_UNDERFLOW 0x40000036 |
| 68 |
#define NATV_BRANCH_EVENT 0x40000037 |
| 69 |
#define NATV_BR_MISPRED_DETAIL_ALL_ALL_PRED 0x40000038 |
| 70 |
#define NATV_BR_MISPRED_DETAIL_ALL_CORRECT_PRED 0x40000039 |
| 71 |
#define NATV_BR_MISPRED_DETAIL_ALL_WRONG_PATH 0x4000003a |
| 72 |
#define NATV_BR_MISPRED_DETAIL_ALL_WRONG_TARGET 0x4000003b |
| 73 |
#define NATV_BR_MISPRED_DETAIL_IPREL_ALL_PRED 0x4000003c |
| 74 |
#define NATV_BR_MISPRED_DETAIL_IPREL_CORRECT_PRED 0x4000003d |
| 75 |
#define NATV_BR_MISPRED_DETAIL_IPREL_WRONG_PATH 0x4000003e |
| 76 |
#define NATV_BR_MISPRED_DETAIL_IPREL_WRONG_TARGET 0x4000003f |
| 77 |
#define NATV_BR_MISPRED_DETAIL_NTRETIND_ALL_PRED 0x40000040 |
| 78 |
#define NATV_BR_MISPRED_DETAIL_NTRETIND_CORRECT_PRED 0x40000041 |
| 79 |
#define NATV_BR_MISPRED_DETAIL_NTRETIND_WRONG_PATH 0x40000042 |
| 80 |
#define NATV_BR_MISPRED_DETAIL_NTRETIND_WRONG_TARGET 0x40000043 |
| 81 |
#define NATV_BR_MISPRED_DETAIL_RETURN_ALL_PRED 0x40000044 |
| 82 |
#define NATV_BR_MISPRED_DETAIL_RETURN_CORRECT_PRED 0x40000045 |
| 83 |
#define NATV_BR_MISPRED_DETAIL_RETURN_WRONG_PATH 0x40000046 |
| 84 |
#define NATV_BR_MISPRED_DETAIL_RETURN_WRONG_TARGET 0x40000047 |
| 85 |
#define NATV_BR_MISPRED_DETAIL2_ALL_ALL_UNKNOWN_PRED 0x40000048 |
| 86 |
#define NATV_BR_MISPRED_DETAIL2_ALL_UNKNOWN_PATH_CORRECT_PRED 0x40000049 |
| 87 |
#define NATV_BR_MISPRED_DETAIL2_ALL_UNKNOWN_PATH_WRONG_PATH 0x4000004a |
| 88 |
#define NATV_BR_MISPRED_DETAIL2_IPREL_ALL_UNKNOWN_PRED 0x4000004b |
| 89 |
#define NATV_BR_MISPRED_DETAIL2_IPREL_UNKNOWN_PATH_CORRECT_PRED 0x4000004c |
| 90 |
#define NATV_BR_MISPRED_DETAIL2_IPREL_UNKNOWN_PATH_WRONG_PATH 0x4000004d |
| 91 |
#define NATV_BR_MISPRED_DETAIL2_NRETIND_ALL_UNKNOWN_PRED 0x4000004e |
| 92 |
#define NATV_BR_MISPRED_DETAIL2_NRETIND_UNKNOWN_PATH_CORRECT_PRED 0x4000004f |
| 93 |
#define NATV_BR_MISPRED_DETAIL2_NRETIND_UNKNOWN_PATH_WRONG_PATH 0x40000050 |
| 94 |
#define NATV_BR_MISPRED_DETAIL2_RETURN_ALL_UNKNOWN_PRED 0x40000051 |
| 95 |
#define NATV_BR_MISPRED_DETAIL2_RETURN_UNKNOWN_PATH_CORRECT_PRED 0x40000052 |
| 96 |
#define NATV_BR_MISPRED_DETAIL2_RETURN_UNKNOWN_PATH_WRONG_PATH 0x40000053 |
| 97 |
#define NATV_BR_PATH_PRED_ALL_MISPRED_NOTTAKEN 0x40000054 |
| 98 |
#define NATV_BR_PATH_PRED_ALL_MISPRED_TAKEN 0x40000055 |
| 99 |
#define NATV_BR_PATH_PRED_ALL_OKPRED_NOTTAKEN 0x40000056 |
| 100 |
#define NATV_BR_PATH_PRED_ALL_OKPRED_TAKEN 0x40000057 |
| 101 |
#define NATV_BR_PATH_PRED_IPREL_MISPRED_NOTTAKEN 0x40000058 |
| 102 |
#define NATV_BR_PATH_PRED_IPREL_MISPRED_TAKEN 0x40000059 |
| 103 |
#define NATV_BR_PATH_PRED_IPREL_OKPRED_NOTTAKEN 0x4000005a |
| 104 |
#define NATV_BR_PATH_PRED_IPREL_OKPRED_TAKEN 0x4000005b |
| 105 |
#define NATV_BR_PATH_PRED_NRETIND_MISPRED_NOTTAKEN 0x4000005c |
| 106 |
#define NATV_BR_PATH_PRED_NRETIND_MISPRED_TAKEN 0x4000005d |
| 107 |
#define NATV_BR_PATH_PRED_NRETIND_OKPRED_NOTTAKEN 0x4000005e |
| 108 |
#define NATV_BR_PATH_PRED_NRETIND_OKPRED_TAKEN 0x4000005f |
| 109 |
#define NATV_BR_PATH_PRED_RETURN_MISPRED_NOTTAKEN 0x40000060 |
| 110 |
#define NATV_BR_PATH_PRED_RETURN_MISPRED_TAKEN 0x40000061 |
| 111 |
#define NATV_BR_PATH_PRED_RETURN_OKPRED_NOTTAKEN 0x40000062 |
| 112 |
#define NATV_BR_PATH_PRED_RETURN_OKPRED_TAKEN 0x40000063 |
| 113 |
#define NATV_BR_PATH_PRED2_ALL_UNKNOWNPRED_NOTTAKEN 0x40000064 |
| 114 |
#define NATV_BR_PATH_PRED2_ALL_UNKNOWNPRED_TAKEN 0x40000065 |
| 115 |
#define NATV_BR_PATH_PRED2_IPREL_UNKNOWNPRED_NOTTAKEN 0x40000066 |
| 116 |
#define NATV_BR_PATH_PRED2_IPREL_UNKNOWNPRED_TAKEN 0x40000067 |
| 117 |
#define NATV_BR_PATH_PRED2_NRETIND_UNKNOWNPRED_NOTTAKEN 0x40000068 |
| 118 |
#define NATV_BR_PATH_PRED2_NRETIND_UNKNOWNPRED_TAKEN 0x40000069 |
| 119 |
#define NATV_BR_PATH_PRED2_RETURN_UNKNOWNPRED_NOTTAKEN 0x4000006a |
| 120 |
#define NATV_BR_PATH_PRED2_RETURN_UNKNOWNPRED_TAKEN 0x4000006b |
| 121 |
#define NATV_BUS_ALL_ANY 0x4000006c |
| 122 |
#define NATV_BUS_ALL_IO 0x4000006d |
| 123 |
#define NATV_BUS_ALL_SELF 0x4000006e |
| 124 |
#define NATV_BUS_BACKSNP_REQ_THIS 0x4000006f |
| 125 |
#define NATV_BUS_BRQ_LIVE_REQ_HI 0x40000070 |
| 126 |
#define NATV_BUS_BRQ_LIVE_REQ_LO 0x40000071 |
| 127 |
#define NATV_BUS_BRQ_REQ_INSERTED 0x40000072 |
| 128 |
#define NATV_BUS_DATA_CYCLE 0x40000073 |
| 129 |
#define NATV_BUS_HITM 0x40000074 |
| 130 |
#define NATV_BUS_IO_ANY 0x40000075 |
| 131 |
#define NATV_BUS_IO_IO 0x40000076 |
| 132 |
#define NATV_BUS_IO_SELF 0x40000077 |
| 133 |
#define NATV_BUS_IOQ_LIVE_REQ_HI 0x40000078 |
| 134 |
#define NATV_BUS_IOQ_LIVE_REQ_LO 0x40000079 |
| 135 |
#define NATV_BUS_LOCK_ANY 0x4000007a |
| 136 |
#define NATV_BUS_LOCK_SELF 0x4000007b |
| 137 |
#define NATV_BUS_MEMORY_ALL_ANY 0x4000007c |
| 138 |
#define NATV_BUS_MEMORY_ALL_IO 0x4000007d |
| 139 |
#define NATV_BUS_MEMORY_ALL_SELF 0x4000007e |
| 140 |
#define NATV_BUS_MEMORY_EQ_128BYTE_ANY 0x4000007f |
| 141 |
#define NATV_BUS_MEMORY_EQ_128BYTE_IO 0x40000080 |
| 142 |
#define NATV_BUS_MEMORY_EQ_128BYTE_SELF 0x40000081 |
| 143 |
#define NATV_BUS_MEMORY_LT_128BYTE_ANY 0x40000082 |
| 144 |
#define NATV_BUS_MEMORY_LT_128BYTE_IO 0x40000083 |
| 145 |
#define NATV_BUS_MEMORY_LT_128BYTE_SELF 0x40000084 |
| 146 |
#define NATV_BUS_MEM_READ_ALL_ANY 0x40000085 |
| 147 |
#define NATV_BUS_MEM_READ_ALL_IO 0x40000086 |
| 148 |
#define NATV_BUS_MEM_READ_ALL_SELF 0x40000087 |
| 149 |
#define NATV_BUS_MEM_READ_BIL_ANY 0x40000088 |
| 150 |
#define NATV_BUS_MEM_READ_BIL_IO 0x40000089 |
| 151 |
#define NATV_BUS_MEM_READ_BIL_SELF 0x4000008a |
| 152 |
#define NATV_BUS_MEM_READ_BRIL_ANY 0x4000008b |
| 153 |
#define NATV_BUS_MEM_READ_BRIL_IO 0x4000008c |
| 154 |
#define NATV_BUS_MEM_READ_BRIL_SELF 0x4000008d |
| 155 |
#define NATV_BUS_MEM_READ_BRL_ANY 0x4000008e |
| 156 |
#define NATV_BUS_MEM_READ_BRL_IO 0x4000008f |
| 157 |
#define NATV_BUS_MEM_READ_BRL_SELF 0x40000090 |
| 158 |
#define NATV_BUS_MEM_READ_OUT_HI 0x40000091 |
| 159 |
#define NATV_BUS_MEM_READ_OUT_LO 0x40000092 |
| 160 |
#define NATV_BUS_OOQ_LIVE_REQ_HI 0x40000093 |
| 161 |
#define NATV_BUS_OOQ_LIVE_REQ_LO 0x40000094 |
| 162 |
#define NATV_BUS_RD_DATA_ANY 0x40000095 |
| 163 |
#define NATV_BUS_RD_DATA_IO 0x40000096 |
| 164 |
#define NATV_BUS_RD_DATA_SELF 0x40000097 |
| 165 |
#define NATV_BUS_RD_HIT 0x40000098 |
| 166 |
#define NATV_BUS_RD_HITM 0x40000099 |
| 167 |
#define NATV_BUS_RD_INVAL_ALL_HITM 0x4000009a |
| 168 |
#define NATV_BUS_RD_INVAL_HITM 0x4000009b |
| 169 |
#define NATV_BUS_RD_IO_ANY 0x4000009c |
| 170 |
#define NATV_BUS_RD_IO_IO 0x4000009d |
| 171 |
#define NATV_BUS_RD_IO_SELF 0x4000009e |
| 172 |
#define NATV_BUS_RD_PRTL_ANY 0x4000009f |
| 173 |
#define NATV_BUS_RD_PRTL_IO 0x400000a0 |
| 174 |
#define NATV_BUS_RD_PRTL_SELF 0x400000a1 |
| 175 |
#define NATV_BUS_SNOOPQ_REQ 0x400000a2 |
| 176 |
#define NATV_BUS_SNOOPS_ANY 0x400000a3 |
| 177 |
#define NATV_BUS_SNOOPS_IO 0x400000a4 |
| 178 |
#define NATV_BUS_SNOOPS_SELF 0x400000a5 |
| 179 |
#define NATV_BUS_SNOOPS_HITM_ANY 0x400000a6 |
| 180 |
#define NATV_BUS_SNOOPS_HITM_SELF 0x400000a7 |
| 181 |
#define NATV_BUS_SNOOP_STALL_CYCLES_ANY 0x400000a8 |
| 182 |
#define NATV_BUS_SNOOP_STALL_CYCLES_SELF 0x400000a9 |
| 183 |
#define NATV_BUS_WR_WB_ALL_ANY 0x400000aa |
| 184 |
#define NATV_BUS_WR_WB_ALL_IO 0x400000ab |
| 185 |
#define NATV_BUS_WR_WB_ALL_SELF 0x400000ac |
| 186 |
#define NATV_BUS_WR_WB_CCASTOUT_ANY 0x400000ad |
| 187 |
#define NATV_BUS_WR_WB_CCASTOUT_SELF 0x400000ae |
| 188 |
#define NATV_BUS_WR_WB_EQ_128BYTE_ANY 0x400000af |
| 189 |
#define NATV_BUS_WR_WB_EQ_128BYTE_IO 0x400000b0 |
| 190 |
#define NATV_BUS_WR_WB_EQ_128BYTE_SELF 0x400000b1 |
| 191 |
#define NATV_CPU_CPL_CHANGES 0x400000b2 |
| 192 |
#define NATV_CPU_CYCLES 0x400000b3 |
| 193 |
#define NATV_DATA_DEBUG_REGISTER_FAULT 0x400000b4 |
| 194 |
#define NATV_DATA_DEBUG_REGISTER_MATCHES 0x400000b5 |
| 195 |
#define NATV_DATA_EAR_ALAT 0x400000b6 |
| 196 |
#define NATV_DATA_EAR_CACHE_LAT1024 0x400000b7 |
| 197 |
#define NATV_DATA_EAR_CACHE_LAT128 0x400000b8 |
| 198 |
#define NATV_DATA_EAR_CACHE_LAT16 0x400000b9 |
| 199 |
#define NATV_DATA_EAR_CACHE_LAT2048 0x400000ba |
| 200 |
#define NATV_DATA_EAR_CACHE_LAT256 0x400000bb |
| 201 |
#define NATV_DATA_EAR_CACHE_LAT32 0x400000bc |
| 202 |
#define NATV_DATA_EAR_CACHE_LAT4 0x400000bd |
| 203 |
#define NATV_DATA_EAR_CACHE_LAT4096 0x400000be |
| 204 |
#define NATV_DATA_EAR_CACHE_LAT512 0x400000bf |
| 205 |
#define NATV_DATA_EAR_CACHE_LAT64 0x400000c0 |
| 206 |
#define NATV_DATA_EAR_CACHE_LAT8 0x400000c1 |
| 207 |
#define NATV_DATA_EAR_EVENTS 0x400000c2 |
| 208 |
#define NATV_DATA_EAR_TLB_ALL 0x400000c3 |
| 209 |
#define NATV_DATA_EAR_TLB_FAULT 0x400000c4 |
| 210 |
#define NATV_DATA_EAR_TLB_L2DTLB 0x400000c5 |
| 211 |
#define NATV_DATA_EAR_TLB_L2DTLB_OR_FAULT 0x400000c6 |
| 212 |
#define NATV_DATA_EAR_TLB_L2DTLB_OR_VHPT 0x400000c7 |
| 213 |
#define NATV_DATA_EAR_TLB_VHPT 0x400000c8 |
| 214 |
#define NATV_DATA_EAR_TLB_VHPT_OR_FAULT 0x400000c9 |
| 215 |
#define NATV_DATA_REFERENCES_SET0 0x400000ca |
| 216 |
#define NATV_DATA_REFERENCES_SET1 0x400000cb |
| 217 |
#define NATV_DISP_STALLED 0x400000cc |
| 218 |
#define NATV_DTLB_INSERTS_HPW 0x400000cd |
| 219 |
#define NATV_DTLB_INSERTS_HPW_RETIRED 0x400000ce |
| 220 |
#define NATV_ENCBR_MISPRED_DETAIL_ALL_ALL_PRED 0x400000cf |
| 221 |
#define NATV_ENCBR_MISPRED_DETAIL_ALL_CORRECT_PRED 0x400000d0 |
| 222 |
#define NATV_ENCBR_MISPRED_DETAIL_ALL_WRONG_PATH 0x400000d1 |
| 223 |
#define NATV_ENCBR_MISPRED_DETAIL_ALL_WRONG_TARGET 0x400000d2 |
| 224 |
#define NATV_ENCBR_MISPRED_DETAIL_ALL2_ALL_PRED 0x400000d3 |
| 225 |
#define NATV_ENCBR_MISPRED_DETAIL_ALL2_CORRECT_PRED 0x400000d4 |
| 226 |
#define NATV_ENCBR_MISPRED_DETAIL_ALL2_WRONG_PATH 0x400000d5 |
| 227 |
#define NATV_ENCBR_MISPRED_DETAIL_ALL2_WRONG_TARGET 0x400000d6 |
| 228 |
#define NATV_ENCBR_MISPRED_DETAIL_OVERSUB_ALL_PRED 0x400000d7 |
| 229 |
#define NATV_ENCBR_MISPRED_DETAIL_OVERSUB_CORRECT_PRED 0x400000d8 |
| 230 |
#define NATV_ENCBR_MISPRED_DETAIL_OVERSUB_WRONG_PATH 0x400000d9 |
| 231 |
#define NATV_ENCBR_MISPRED_DETAIL_OVERSUB_WRONG_TARGET 0x400000da |
| 232 |
#define NATV_EXTERN_DP_PINS_0_TO_3_ALL 0x400000db |
| 233 |
#define NATV_EXTERN_DP_PINS_0_TO_3_PIN0 0x400000dc |
| 234 |
#define NATV_EXTERN_DP_PINS_0_TO_3_PIN0_OR_PIN1 0x400000dd |
| 235 |
#define NATV_EXTERN_DP_PINS_0_TO_3_PIN0_OR_PIN1_OR_PIN2 0x400000de |
| 236 |
#define NATV_EXTERN_DP_PINS_0_TO_3_PIN0_OR_PIN1_OR_PIN3 0x400000df |
| 237 |
#define NATV_EXTERN_DP_PINS_0_TO_3_PIN0_OR_PIN2 0x400000e0 |
| 238 |
#define NATV_EXTERN_DP_PINS_0_TO_3_PIN0_OR_PIN2_OR_PIN3 0x400000e1 |
| 239 |
#define NATV_EXTERN_DP_PINS_0_TO_3_PIN0_OR_PIN3 0x400000e2 |
| 240 |
#define NATV_EXTERN_DP_PINS_0_TO_3_PIN1 0x400000e3 |
| 241 |
#define NATV_EXTERN_DP_PINS_0_TO_3_PIN1_OR_PIN2 0x400000e4 |
| 242 |
#define NATV_EXTERN_DP_PINS_0_TO_3_PIN1_OR_PIN2_OR_PIN3 0x400000e5 |
| 243 |
#define NATV_EXTERN_DP_PINS_0_TO_3_PIN1_OR_PIN3 0x400000e6 |
| 244 |
#define NATV_EXTERN_DP_PINS_0_TO_3_PIN2 0x400000e7 |
| 245 |
#define NATV_EXTERN_DP_PINS_0_TO_3_PIN2_OR_PIN3 0x400000e8 |
| 246 |
#define NATV_EXTERN_DP_PINS_0_TO_3_PIN3 0x400000e9 |
| 247 |
#define NATV_EXTERN_DP_PINS_4_TO_5_ALL 0x400000ea |
| 248 |
#define NATV_EXTERN_DP_PINS_4_TO_5_PIN4 0x400000eb |
| 249 |
#define NATV_EXTERN_DP_PINS_4_TO_5_PIN5 0x400000ec |
| 250 |
#define NATV_FE_BUBBLE_ALL 0x400000ed |
| 251 |
#define NATV_FE_BUBBLE_ALLBUT_FEFLUSH_BUBBLE 0x400000ee |
| 252 |
#define NATV_FE_BUBBLE_ALLBUT_IBFULL 0x400000ef |
| 253 |
#define NATV_FE_BUBBLE_BRANCH 0x400000f0 |
| 254 |
#define NATV_FE_BUBBLE_BUBBLE 0x400000f1 |
| 255 |
#define NATV_FE_BUBBLE_FEFLUSH 0x400000f2 |
| 256 |
#define NATV_FE_BUBBLE_FILL_RECIRC 0x400000f3 |
| 257 |
#define NATV_FE_BUBBLE_GROUP1 0x400000f4 |
| 258 |
#define NATV_FE_BUBBLE_GROUP2 0x400000f5 |
| 259 |
#define NATV_FE_BUBBLE_GROUP3 0x400000f6 |
| 260 |
#define NATV_FE_BUBBLE_IBFULL 0x400000f7 |
| 261 |
#define NATV_FE_BUBBLE_IMISS 0x400000f8 |
| 262 |
#define NATV_FE_BUBBLE_TLBMISS 0x400000f9 |
| 263 |
#define NATV_FE_LOST_BW_ALL 0x400000fa |
| 264 |
#define NATV_FE_LOST_BW_BI 0x400000fb |
| 265 |
#define NATV_FE_LOST_BW_BRQ 0x400000fc |
| 266 |
#define NATV_FE_LOST_BW_BR_ILOCK 0x400000fd |
| 267 |
#define NATV_FE_LOST_BW_BUBBLE 0x400000fe |
| 268 |
#define NATV_FE_LOST_BW_FEFLUSH 0x400000ff |
| 269 |
#define NATV_FE_LOST_BW_FILL_RECIRC 0x40000100 |
| 270 |
#define NATV_FE_LOST_BW_IBFULL 0x40000101 |
| 271 |
#define NATV_FE_LOST_BW_IMISS 0x40000102 |
| 272 |
#define NATV_FE_LOST_BW_PLP 0x40000103 |
| 273 |
#define NATV_FE_LOST_BW_TLBMISS 0x40000104 |
| 274 |
#define NATV_FE_LOST_BW_UNREACHED 0x40000105 |
| 275 |
#define NATV_FP_FAILED_FCHKF 0x40000106 |
| 276 |
#define NATV_FP_FALSE_SIRSTALL 0x40000107 |
| 277 |
#define NATV_FP_FLUSH_TO_ZERO 0x40000108 |
| 278 |
#define NATV_FP_OPS_RETIRED 0x40000109 |
| 279 |
#define NATV_FP_TRUE_SIRSTALL 0x4000010a |
| 280 |
#define NATV_HPW_DATA_REFERENCES 0x4000010b |
| 281 |
#define NATV_IA32_INST_RETIRED 0x4000010c |
| 282 |
#define NATV_IA32_ISA_TRANSITIONS 0x4000010d |
| 283 |
#define NATV_IA64_INST_RETIRED 0x4000010e |
| 284 |
#define NATV_IA64_INST_RETIRED_THIS 0x4000010f |
| 285 |
#define NATV_IA64_TAGGED_INST_RETIRED_IBRP0_PMC8 0x40000110 |
| 286 |
#define NATV_IA64_TAGGED_INST_RETIRED_IBRP1_PMC9 0x40000111 |
| 287 |
#define NATV_IA64_TAGGED_INST_RETIRED_IBRP2_PMC8 0x40000112 |
| 288 |
#define NATV_IA64_TAGGED_INST_RETIRED_IBRP3_PMC9 0x40000113 |
| 289 |
#define NATV_IDEAL_BE_LOST_BW_DUE_TO_FE_ALL 0x40000114 |
| 290 |
#define NATV_IDEAL_BE_LOST_BW_DUE_TO_FE_BI 0x40000115 |
| 291 |
#define NATV_IDEAL_BE_LOST_BW_DUE_TO_FE_BRQ 0x40000116 |
| 292 |
#define NATV_IDEAL_BE_LOST_BW_DUE_TO_FE_BR_ILOCK 0x40000117 |
| 293 |
#define NATV_IDEAL_BE_LOST_BW_DUE_TO_FE_BUBBLE 0x40000118 |
| 294 |
#define NATV_IDEAL_BE_LOST_BW_DUE_TO_FE_FEFLUSH 0x40000119 |
| 295 |
#define NATV_IDEAL_BE_LOST_BW_DUE_TO_FE_FILL_RECIRC 0x4000011a |
| 296 |
#define NATV_IDEAL_BE_LOST_BW_DUE_TO_FE_IBFULL 0x4000011b |
| 297 |
#define NATV_IDEAL_BE_LOST_BW_DUE_TO_FE_IMISS 0x4000011c |
| 298 |
#define NATV_IDEAL_BE_LOST_BW_DUE_TO_FE_PLP 0x4000011d |
| 299 |
#define NATV_IDEAL_BE_LOST_BW_DUE_TO_FE_TLBMISS 0x4000011e |
| 300 |
#define NATV_IDEAL_BE_LOST_BW_DUE_TO_FE_UNREACHED 0x4000011f |
| 301 |
#define NATV_INST_CHKA_LDC_ALAT_ALL 0x40000120 |
| 302 |
#define NATV_INST_CHKA_LDC_ALAT_FP 0x40000121 |
| 303 |
#define NATV_INST_CHKA_LDC_ALAT_INT 0x40000122 |
| 304 |
#define NATV_INST_DISPERSED 0x40000123 |
| 305 |
#define NATV_INST_FAILED_CHKA_LDC_ALAT_ALL 0x40000124 |
| 306 |
#define NATV_INST_FAILED_CHKA_LDC_ALAT_FP 0x40000125 |
| 307 |
#define NATV_INST_FAILED_CHKA_LDC_ALAT_INT 0x40000126 |
| 308 |
#define NATV_INST_FAILED_CHKS_RETIRED_ALL 0x40000127 |
| 309 |
#define NATV_INST_FAILED_CHKS_RETIRED_FP 0x40000128 |
| 310 |
#define NATV_INST_FAILED_CHKS_RETIRED_INT 0x40000129 |
| 311 |
#define NATV_ISB_BUNPAIRS_IN 0x4000012a |
| 312 |
#define NATV_ITLB_MISSES_FETCH_ALL 0x4000012b |
| 313 |
#define NATV_ITLB_MISSES_FETCH_L1ITLB 0x4000012c |
| 314 |
#define NATV_ITLB_MISSES_FETCH_L2ITLB 0x4000012d |
| 315 |
#define NATV_L1DTLB_TRANSFER 0x4000012e |
| 316 |
#define NATV_L1D_READS_SET0 0x4000012f |
| 317 |
#define NATV_L1D_READS_SET1 0x40000130 |
| 318 |
#define NATV_L1D_READ_MISSES_ALL 0x40000131 |
| 319 |
#define NATV_L1D_READ_MISSES_RSE_FILL 0x40000132 |
| 320 |
#define NATV_L1ITLB_INSERTS_HPW 0x40000133 |
| 321 |
#define NATV_L1I_EAR_CACHE_LAT0 0x40000134 |
| 322 |
#define NATV_L1I_EAR_CACHE_LAT1024 0x40000135 |
| 323 |
#define NATV_L1I_EAR_CACHE_LAT128 0x40000136 |
| 324 |
#define NATV_L1I_EAR_CACHE_LAT16 0x40000137 |
| 325 |
#define NATV_L1I_EAR_CACHE_LAT256 0x40000138 |
| 326 |
#define NATV_L1I_EAR_CACHE_LAT32 0x40000139 |
| 327 |
#define NATV_L1I_EAR_CACHE_LAT4 0x4000013a |
| 328 |
#define NATV_L1I_EAR_CACHE_LAT4096 0x4000013b |
| 329 |
#define NATV_L1I_EAR_CACHE_LAT8 0x4000013c |
| 330 |
#define NATV_L1I_EAR_CACHE_RAB 0x4000013d |
| 331 |
#define NATV_L1I_EAR_EVENTS 0x4000013e |
| 332 |
#define NATV_L1I_EAR_TLB_ALL 0x4000013f |
| 333 |
#define NATV_L1I_EAR_TLB_FAULT 0x40000140 |
| 334 |
#define NATV_L1I_EAR_TLB_L2TLB 0x40000141 |
| 335 |
#define NATV_L1I_EAR_TLB_L2TLB_OR_FAULT 0x40000142 |
| 336 |
#define NATV_L1I_EAR_TLB_L2TLB_OR_VHPT 0x40000143 |
| 337 |
#define NATV_L1I_EAR_TLB_VHPT 0x40000144 |
| 338 |
#define NATV_L1I_EAR_TLB_VHPT_OR_FAULT 0x40000145 |
| 339 |
#define NATV_L1I_FETCH_ISB_HIT 0x40000146 |
| 340 |
#define NATV_L1I_FETCH_RAB_HIT 0x40000147 |
| 341 |
#define NATV_L1I_FILLS 0x40000148 |
| 342 |
#define NATV_L1I_PREFETCHES 0x40000149 |
| 343 |
#define NATV_L1I_PREFETCH_STALL_ALL 0x4000014a |
| 344 |
#define NATV_L1I_PREFETCH_STALL_FLOW 0x4000014b |
| 345 |
#define NATV_L1I_PURGE 0x4000014c |
| 346 |
#define NATV_L1I_PVAB_OVERFLOW 0x4000014d |
| 347 |
#define NATV_L1I_RAB_ALMOST_FULL 0x4000014e |
| 348 |
#define NATV_L1I_RAB_FULL 0x4000014f |
| 349 |
#define NATV_L1I_READS 0x40000150 |
| 350 |
#define NATV_L1I_SNOOP 0x40000151 |
| 351 |
#define NATV_L1I_STRM_PREFETCHES 0x40000152 |
| 352 |
#define NATV_L2DTLB_MISSES 0x40000153 |
| 353 |
#define NATV_L2_BAD_LINES_SELECTED_ANY 0x40000154 |
| 354 |
#define NATV_L2_BYPASS_L2_DATA1 0x40000155 |
| 355 |
#define NATV_L2_BYPASS_L2_DATA2 0x40000156 |
| 356 |
#define NATV_L2_BYPASS_L2_INST1 0x40000157 |
| 357 |
#define NATV_L2_BYPASS_L2_INST2 0x40000158 |
| 358 |
#define NATV_L2_BYPASS_L3_DATA1 0x40000159 |
| 359 |
#define NATV_L2_BYPASS_L3_INST1 0x4000015a |
| 360 |
#define NATV_L2_DATA_REFERENCES_L2_ALL 0x4000015b |
| 361 |
#define NATV_L2_DATA_REFERENCES_L2_DATA_READS 0x4000015c |
| 362 |
#define NATV_L2_DATA_REFERENCES_L2_DATA_WRITES 0x4000015d |
| 363 |
#define NATV_L2_FILLB_FULL_THIS 0x4000015e |
| 364 |
#define NATV_L2_FORCE_RECIRC_ANY 0x4000015f |
| 365 |
#define NATV_L2_FORCE_RECIRC_FILL_HIT 0x40000160 |
| 366 |
#define NATV_L2_FORCE_RECIRC_FRC_RECIRC 0x40000161 |
| 367 |
#define NATV_L2_FORCE_RECIRC_IPF_MISS 0x40000162 |
| 368 |
#define NATV_L2_FORCE_RECIRC_L1W 0x40000163 |
| 369 |
#define NATV_L2_FORCE_RECIRC_OZQ_MISS 0x40000164 |
| 370 |
#define NATV_L2_FORCE_RECIRC_SAME_INDEX 0x40000165 |
| 371 |
#define NATV_L2_FORCE_RECIRC_SMC_HIT 0x40000166 |
| 372 |
#define NATV_L2_FORCE_RECIRC_SNP_OR_L3 0x40000167 |
| 373 |
#define NATV_L2_FORCE_RECIRC_TAG_NOTOK 0x40000168 |
| 374 |
#define NATV_L2_FORCE_RECIRC_TRAN_PREF 0x40000169 |
| 375 |
#define NATV_L2_FORCE_RECIRC_VIC_BUF_FULL 0x4000016a |
| 376 |
#define NATV_L2_FORCE_RECIRC_VIC_PEND 0x4000016b |
| 377 |
#define NATV_L2_GOT_RECIRC_IFETCH_ANY 0x4000016c |
| 378 |
#define NATV_L2_GOT_RECIRC_OZQ_ACC 0x4000016d |
| 379 |
#define NATV_L2_IFET_CANCELS_ANY 0x4000016e |
| 380 |
#define NATV_L2_IFET_CANCELS_BYPASS 0x4000016f |
| 381 |
#define NATV_L2_IFET_CANCELS_CHG_PRIO 0x40000170 |
| 382 |
#define NATV_L2_IFET_CANCELS_DATA_RD 0x40000171 |
| 383 |
#define NATV_L2_IFET_CANCELS_DIDNT_RECIR 0x40000172 |
| 384 |
#define NATV_L2_IFET_CANCELS_IFETCH_BYP 0x40000173 |
| 385 |
#define NATV_L2_IFET_CANCELS_PREEMPT 0x40000174 |
| 386 |
#define NATV_L2_IFET_CANCELS_RECIR_OVER_SUB 0x40000175 |
| 387 |
#define NATV_L2_IFET_CANCELS_ST_FILL_WB 0x40000176 |
| 388 |
#define NATV_L2_INST_DEMAND_READS 0x40000177 |
| 389 |
#define NATV_L2_INST_PREFETCHES 0x40000178 |
| 390 |
#define NATV_L2_ISSUED_RECIRC_IFETCH_ANY 0x40000179 |
| 391 |
#define NATV_L2_ISSUED_RECIRC_OZQ_ACC 0x4000017a |
| 392 |
#define NATV_L2_L3ACCESS_CANCEL_ANY 0x4000017b |
| 393 |
#define NATV_L2_L3ACCESS_CANCEL_DFETCH 0x4000017c |
| 394 |
#define NATV_L2_L3ACCESS_CANCEL_EBL_REJECT 0x4000017d |
| 395 |
#define NATV_L2_L3ACCESS_CANCEL_FILLD_FULL 0x4000017e |
| 396 |
#define NATV_L2_L3ACCESS_CANCEL_IFETCH 0x4000017f |
| 397 |
#define NATV_L2_L3ACCESS_CANCEL_INV_L3_BYP 0x40000180 |
| 398 |
#define NATV_L2_L3ACCESS_CANCEL_SPEC_L3_BYP 0x40000181 |
| 399 |
#define NATV_L2_L3ACCESS_CANCEL_UC_BLOCKED 0x40000182 |
| 400 |
#define NATV_L2_MISSES 0x40000183 |
| 401 |
#define NATV_L2_OPS_ISSUED_FP_LOAD 0x40000184 |
| 402 |
#define NATV_L2_OPS_ISSUED_INT_LOAD 0x40000185 |
| 403 |
#define NATV_L2_OPS_ISSUED_NST_NLD 0x40000186 |
| 404 |
#define NATV_L2_OPS_ISSUED_RMW 0x40000187 |
| 405 |
#define NATV_L2_OPS_ISSUED_STORE 0x40000188 |
| 406 |
#define NATV_L2_OZDB_FULL_THIS 0x40000189 |
| 407 |
#define NATV_L2_OZQ_ACQUIRE 0x4000018a |
| 408 |
#define NATV_L2_OZQ_CANCELS0_ANY 0x4000018b |
| 409 |
#define NATV_L2_OZQ_CANCELS0_LATE_ACQUIRE 0x4000018c |
| 410 |
#define NATV_L2_OZQ_CANCELS0_LATE_BYP_EFFRELEASE 0x4000018d |
| 411 |
#define NATV_L2_OZQ_CANCELS0_LATE_RELEASE 0x4000018e |
| 412 |
#define NATV_L2_OZQ_CANCELS0_LATE_SPEC_BYP 0x4000018f |
| 413 |
#define NATV_L2_OZQ_CANCELS1_BANK_CONF 0x40000190 |
| 414 |
#define NATV_L2_OZQ_CANCELS1_CANC_L2M_ST 0x40000191 |
| 415 |
#define NATV_L2_OZQ_CANCELS1_CCV 0x40000192 |
| 416 |
#define NATV_L2_OZQ_CANCELS1_ECC 0x40000193 |
| 417 |
#define NATV_L2_OZQ_CANCELS1_HPW_IFETCH_CONF 0x40000194 |
| 418 |
#define NATV_L2_OZQ_CANCELS1_L1DF_L2M 0x40000195 |
| 419 |
#define NATV_L2_OZQ_CANCELS1_L1_FILL_CONF 0x40000196 |
| 420 |
#define NATV_L2_OZQ_CANCELS1_L2A_ST_MAT 0x40000197 |
| 421 |
#define NATV_L2_OZQ_CANCELS1_L2D_ST_MAT 0x40000198 |
| 422 |
#define NATV_L2_OZQ_CANCELS1_L2M_ST_MAT 0x40000199 |
| 423 |
#define NATV_L2_OZQ_CANCELS1_MFA 0x4000019a |
| 424 |
#define NATV_L2_OZQ_CANCELS1_REL 0x4000019b |
| 425 |
#define NATV_L2_OZQ_CANCELS1_SEM 0x4000019c |
| 426 |
#define NATV_L2_OZQ_CANCELS1_ST_FILL_CONF 0x4000019d |
| 427 |
#define NATV_L2_OZQ_CANCELS1_SYNC 0x4000019e |
| 428 |
#define NATV_L2_OZQ_CANCELS2_ACQ 0x4000019f |
| 429 |
#define NATV_L2_OZQ_CANCELS2_CANC_L2C_ST 0x400001a0 |
| 430 |
#define NATV_L2_OZQ_CANCELS2_CANC_L2D_ST 0x400001a1 |
| 431 |
#define NATV_L2_OZQ_CANCELS2_DIDNT_RECIRC 0x400001a2 |
| 432 |
#define NATV_L2_OZQ_CANCELS2_D_IFET 0x400001a3 |
| 433 |
#define NATV_L2_OZQ_CANCELS2_L2C_ST_MAT 0x400001a4 |
| 434 |
#define NATV_L2_OZQ_CANCELS2_L2FILL_ST_CONF 0x400001a5 |
| 435 |
#define NATV_L2_OZQ_CANCELS2_OVER_SUB 0x400001a6 |
| 436 |
#define NATV_L2_OZQ_CANCELS2_OZ_DATA_CONF 0x400001a7 |
| 437 |
#define NATV_L2_OZQ_CANCELS2_READ_WB_CONF 0x400001a8 |
| 438 |
#define NATV_L2_OZQ_CANCELS2_RECIRC_OVER_SUB 0x400001a9 |
| 439 |
#define NATV_L2_OZQ_CANCELS2_SCRUB 0x400001aa |
| 440 |
#define NATV_L2_OZQ_CANCELS2_WEIRD 0x400001ab |
| 441 |
#define NATV_L2_OZQ_FULL_THIS 0x400001ac |
| 442 |
#define NATV_L2_OZQ_RELEASE 0x400001ad |
| 443 |
#define NATV_L2_REFERENCES 0x400001ae |
| 444 |
#define NATV_L2_STORE_HIT_SHARED_ANY 0x400001af |
| 445 |
#define NATV_L2_SYNTH_PROBE 0x400001b0 |
| 446 |
#define NATV_L2_VICTIMB_FULL_THIS 0x400001b1 |
| 447 |
#define NATV_L3_LINES_REPLACED 0x400001b2 |
| 448 |
#define NATV_L3_MISSES 0x400001b3 |
| 449 |
#define NATV_L3_READS_ALL_ALL 0x400001b4 |
| 450 |
#define NATV_L3_READS_ALL_HIT 0x400001b5 |
| 451 |
#define NATV_L3_READS_ALL_MISS 0x400001b6 |
| 452 |
#define NATV_L3_READS_DATA_READ_ALL 0x400001b7 |
| 453 |
#define NATV_L3_READS_DATA_READ_HIT 0x400001b8 |
| 454 |
#define NATV_L3_READS_DATA_READ_MISS 0x400001b9 |
| 455 |
#define NATV_L3_READS_DINST_FETCH_ALL 0x400001ba |
| 456 |
#define NATV_L3_READS_DINST_FETCH_HIT 0x400001bb |
| 457 |
#define NATV_L3_READS_DINST_FETCH_MISS 0x400001bc |
| 458 |
#define NATV_L3_READS_INST_FETCH_ALL 0x400001bd |
| 459 |
#define NATV_L3_READS_INST_FETCH_HIT 0x400001be |
| 460 |
#define NATV_L3_READS_INST_FETCH_MISS 0x400001bf |
| 461 |
#define NATV_L3_REFERENCES 0x400001c0 |
| 462 |
#define NATV_L3_WRITES_ALL_ALL 0x400001c1 |
| 463 |
#define NATV_L3_WRITES_ALL_HIT 0x400001c2 |
| 464 |
#define NATV_L3_WRITES_ALL_MISS 0x400001c3 |
| 465 |
#define NATV_L3_WRITES_DATA_WRITE_ALL 0x400001c4 |
| 466 |
#define NATV_L3_WRITES_DATA_WRITE_HIT 0x400001c5 |
| 467 |
#define NATV_L3_WRITES_DATA_WRITE_MISS 0x400001c6 |
| 468 |
#define NATV_L3_WRITES_L2_WB_ALL 0x400001c7 |
| 469 |
#define NATV_L3_WRITES_L2_WB_HIT 0x400001c8 |
| 470 |
#define NATV_L3_WRITES_L2_WB_MISS 0x400001c9 |
| 471 |
#define NATV_LOADS_RETIRED 0x400001ca |
| 472 |
#define NATV_MEM_READ_CURRENT_ANY 0x400001cb |
| 473 |
#define NATV_MEM_READ_CURRENT_IO 0x400001cc |
| 474 |
#define NATV_MISALIGNED_LOADS_RETIRED 0x400001cd |
| 475 |
#define NATV_MISALIGNED_STORES_RETIRED 0x400001ce |
| 476 |
#define NATV_NOPS_RETIRED 0x400001cf |
| 477 |
#define NATV_PREDICATE_SQUASHED_RETIRED 0x400001d0 |
| 478 |
#define NATV_RSE_CURRENT_REGS_2_TO_0 0x400001d1 |
| 479 |
#define NATV_RSE_CURRENT_REGS_5_TO_3 0x400001d2 |
| 480 |
#define NATV_RSE_CURRENT_REGS_6 0x400001d3 |
| 481 |
#define NATV_RSE_DIRTY_REGS_2_TO_0 0x400001d4 |
| 482 |
#define NATV_RSE_DIRTY_REGS_5_TO_3 0x400001d5 |
| 483 |
#define NATV_RSE_DIRTY_REGS_6 0x400001d6 |
| 484 |
#define NATV_RSE_EVENT_RETIRED 0x400001d7 |
| 485 |
#define NATV_RSE_REFERENCES_RETIRED_ALL 0x400001d8 |
| 486 |
#define NATV_RSE_REFERENCES_RETIRED_LOAD 0x400001d9 |
| 487 |
#define NATV_RSE_REFERENCES_RETIRED_STORE 0x400001da |
| 488 |
#define NATV_SERIALIZATION_EVENTS 0x400001db |
| 489 |
#define NATV_STORES_RETIRED 0x400001dc |
| 490 |
#define NATV_SYLL_NOT_DISPERSED_ALL 0x400001dd |
| 491 |
#define NATV_SYLL_NOT_DISPERSED_EXPL 0x400001de |
| 492 |
#define NATV_SYLL_NOT_DISPERSED_EXPL_OR_FE 0x400001df |
| 493 |
#define NATV_SYLL_NOT_DISPERSED_EXPL_OR_FE_OR_MLI 0x400001e0 |
| 494 |
#define NATV_SYLL_NOT_DISPERSED_EXPL_OR_IMPL 0x400001e1 |
| 495 |
#define NATV_SYLL_NOT_DISPERSED_EXPL_OR_IMPL_OR_FE 0x400001e2 |
| 496 |
#define NATV_SYLL_NOT_DISPERSED_EXPL_OR_IMPL_OR_MLI 0x400001e3 |
| 497 |
#define NATV_SYLL_NOT_DISPERSED_EXPL_OR_MLI 0x400001e4 |
| 498 |
#define NATV_SYLL_NOT_DISPERSED_FE 0x400001e5 |
| 499 |
#define NATV_SYLL_NOT_DISPERSED_FE_OR_MLI 0x400001e6 |
| 500 |
#define NATV_SYLL_NOT_DISPERSED_IMPL 0x400001e7 |
| 501 |
#define NATV_SYLL_NOT_DISPERSED_IMPL_OR_FE 0x400001e8 |
| 502 |
#define NATV_SYLL_NOT_DISPERSED_IMPL_OR_FE_OR_MLI 0x400001e9 |
| 503 |
#define NATV_SYLL_NOT_DISPERSED_IMPL_OR_MLI 0x400001ea |
| 504 |
#define NATV_SYLL_NOT_DISPERSED_MLI 0x400001eb |
| 505 |
#define NATV_SYLL_OVERCOUNT_ALL 0x400001ec |
| 506 |
#define NATV_SYLL_OVERCOUNT_EXPL 0x400001ed |
| 507 |
#define NATV_SYLL_OVERCOUNT_IMPL 0x400001ee |
| 508 |
#define NATV_UC_LOADS_RETIRED 0x400001ef |
| 509 |
#define NATV_UC_STORES_RETIRED 0x400001f0 |
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